Circuitized substrates, such as chip carriers, have been and continue to be developed for many applications. A circuitized substrate, such as an organic chip carrier for interconnecting a semiconductor chip to a printed circuit board in an electronic package, may have a surface redistribution layer for redistributing electrical signals from the circuitized substrate into a larger area so that the circuitized substrate can properly interface with the printed circuit board. A solder mask may be positioned on the redistribution layer.
As semiconductor chip input/output (I/O) count increases beyond the capability of peripheral lead devices and as the need for both semiconductor chip and printed circuit board miniaturization increases, area array interconnects will be the preferred method for making large number of connections between a chip carrier and a printed circuit board. For circuitized organic substrates, including chip carriers and printed circuit boards, it is known that the materials making up these substrates have some flexibility. All flexible materials have some limitations on the amount of mechanical strain which can be tolerated until the material fractures and fails. A measure of this is commonly known as ductility. During manufacture of an electronic package and its assembly to a printed circuit board, many sources of chip carrier and printed circuit board flexure or bending exist. Sources include manual handling through assembly, placing the printed circuit board into tooling fixtures, assembling other components onto the printed circuit board, assembly of cables and hardware to the printed circuit board and use of pressure-probes for electrical testing. Furthermore, if the coefficient of thermal expansion (CTE) of the semiconductor chip, the chip carrier, and the printed circuit board are substantially different from one another, temperature changes during operation of the electronic package can cause flexure or bending of the organic structures by different amounts. As a result, industry standard ball grid array (BGA) interconnections between the chip carrier and printed circuit board may be subject to high stress. These high stresses can be transmitted into the chip carrier and can potentially cause high strain on the chip carrier materials beyond the limits of their ductility, and cause damage in the chip carrier. Significant yield loss concerns during manufacturing, and reliability concerns during thermal cycling field operation may become manifest by failure (cracking or delamination) of dielectrics and circuitry on or within the chip carrier or even failure of the integrity of the semiconductor chip (chip cracking) caused by high stress during manufacturing and field operation. These concerns significantly inhibit design flexibility. For example, semiconductor chip sizes may be limited or interconnect sizes, shapes and spacing may have to be customized outside or beyond industry standards to reduce these stresses. These limitations may limit the electrical performance advantages of the electronic package and/or add significant cost to the electronic package.
A particular yield and reliability concern is that of the surface redistribution layer, which electrically interfaces between the chip carrier and the printed circuit board, and the solder mask layer positioned on the redistribution layer. These layers may be susceptible to stresses transmitted from the printed circuit through the BGA solder ball interconnections from handling or thermal cycling of the electronic package. If the redistribution layer and solder mask layer cannot accommodate the stresses, then they are susceptible to deterioration, such as cracking, which can cause failure of the electronic package. High stresses transmitted to these layers will occur at the edges of the BGA interconnection pads and will be highest at the edges of the BGA interconnection pads under the rows of BGA solder ball interconnections at or near a corner of the chip carrier. To a lesser extent, high stresses transmitted to these layers can occur at the edges of the BGA interconnection pads under the rows of BGA solder ball interconnections at or near the non corner edges of the chip carrier. Cracks in the solder mask and redistribution layer caused by the flexure, described above, generally initiate in these areas of highest stress. Solutions to this problem which limit or reduce the amount of printed circuit board flexure can be impractical and overly restrictive.
FIG. 1A shows a much enlarged bottom view of a portion of a prior art chip carrier 10. FIG. 1B shows a much enlarged view, in elevation of the portion of prior art chip carrier 10, taken along line 1B—1B in FIG. 1A. The chip carrier 10 includes a circuitized substrate 12 having a first surface 14 and a first circuit pattern 16 on the first surface. First circuit pattern 16 can also be referred to as a redistribution layer. An insulating layer 18 is on first surface 14 of circuitized substrate 12 and on first circuit pattern 16. Insulating layer 18 includes an upper surface 20. A second circuit pattern 22 is electrically connected to first circuit pattern 16 by a conductive aperture 24 and is on upper surface 20 of first insulating layer 18 so as to only partially cover first circuit pattern 16. An electrical element 26, for example a solder ball, is on second circuit pattern 22, and makes electrical contact with the second circuit pattern. A portion of a printed circuit board 28, shown in phantom, is electrically coupled to electrical element 26. As described above, flexure or bending of printed circuit board 28 can lead to stresses imparted into electrical element 26. A high stress will occur at the edge p1 of second circuit pattern 22. When electrical element 26 is one of an array (not shown) of solder ball interconnections, the highest stresses will occur at the corner regions, and to a lesser extent at the non corner edge regions, of the array of solder ball interconnections at the edge p1 of second circuit pattern 22. As a result of these high stresses, a crack p3 can develop in insulating layer 18. Stress can then be concentrated on first circuit pattern 16 eventually resulting in a crack p4 in the first circuit pattern, creating an electrical open. Yield and reliability of the chip carrier and the electronic package of which it is a part can be negatively affected.
Thus it is desirable to have a flexible chip carrier that substantially inhibits or prevents cracking of the first circuit pattern during flexure of the chip carrier caused by assembly, handling or operation. Chip carriers of this type will have improved yield and increased operational field life.